The present invention relates generally to integrated circuit memory devices and, more particularly, to port enable signal generation for gating a memory array device output.
As will be appreciated by those skilled in the art, in a domino Static Random Access Memory (SRAM), the individual cells do not employ sense amplifiers to sense the differential voltage on the bit line pairs coupled to the cross-coupled inverters that store the data. Rather, for a domino SRAM, the local bit line is precharged, discharged, and the discharge is detected. The local bit line, the means to precharge the local bit line, and the detector define a dynamic node of the domino SRAM. An output latch, such as a jam latch or keeper latch is used to capture data output from a domino SRAM. The jam latch temporarily holds the data so that a subsequent device or circuit can read the data.
In order to prevent fast arriving data from the array from being written into the output latch (and corrupting the previous cycle's data), a port enable signal may be generated for controlling a transmission gate coupled between the array output and the output latch. More specifically, the port enable signal is a domino signal that is used as the gate signal for one or more transmission gates in order to gate the array output to the output latch. Since an early array output (for example, from fast read or write through) could corrupt the output latch contents or cause an undesirable power increase (fighting the restore before evaluate), gating with the port enable signal allows subsequent logic using the output latch contents to have an expanded sample time. On the other hand, another way to prevent fast write data from being written to the output latch may be to use a read enable signal to gate off write data. However, gating off write data would still not prevent a fast cell's read data from causing hold time problems (latch corruption or power increase) at the latch.